Designed and verified a custom System-on-Chip (SoC) based on the RISC-V architecture, specifically optimized for high-fidelity audio processing. By utilizing a single-cycle datapath, the system ensures cycle-perfect determinism, eliminating the sample jitter commonly found in more complex pipelined processors.
Standard OS-based audio processing suffers from non-deterministic latency caused by interrupts and context switching. To achieve high-fidelity output, the hardware must guarantee that audio samples are delivered to the PWM engine at precise intervals. My goal was to build a "Silicon-Up" solution where the hardware timer forces the CPU to prioritize audio updates via low-level hardware interrupts.
Implemented an RV32I Core in SystemVerilog. Key features include:
0x20 upon timer IRQ.Audio PWM Engine: A custom 8-bit digital-to-analog pulse-width modulator that transforms PCM data into speaker-ready signals. It includes hardware-level saturation logic to prevent digital clipping distortion during high-volume transients.
Programmable Timer: Acts as the system's "Heartbeat," mapped to MMIO address 0x500, allowing software to dynamically adjust the sample rate.
Built a professional verification environment on macOS using Verilator to transpile RTL into high-speed C++ models. Managed complex environment headers (SDKROOT) and automated the build flow with a custom Makefile system to generate VCD (Value Change Dump) files for nanosecond-level waveform debugging in GTKWave.
Sample Jitter
ISA Compliance
IRQ Latency