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Custom Audio SoC RISC-V

RTL Design • SoC Architecture • Firmware Engineering • 2026

SystemVerilog RISC-V ISA Verilator Bare-Metal ASM

Project Overview

Designed and verified a custom System-on-Chip (SoC) based on the RISC-V architecture, specifically optimized for high-fidelity audio processing. By utilizing a single-cycle datapath, the system ensures cycle-perfect determinism, eliminating the sample jitter commonly found in more complex pipelined processors.

The Challenge

Standard OS-based audio processing suffers from non-deterministic latency caused by interrupts and context switching. To achieve high-fidelity output, the hardware must guarantee that audio samples are delivered to the PWM engine at precise intervals. My goal was to build a "Silicon-Up" solution where the hardware timer forces the CPU to prioritize audio updates via low-level hardware interrupts.

Technical Approach

CPU Core & Interrupt Logic

Implemented an RV32I Core in SystemVerilog. Key features include:

  • Hardware Vector Table: CPU immediately jumps to 0x20 upon timer IRQ.
  • Context Saving: Integrated a Machine Exception Program Counter (MEPC) to resume background tasks seamlessly after audio interrupts.
  • Deterministic Execution: Single-cycle ALU ensures predictable instruction latency.

Audio Peripheral Design

Audio PWM Engine: A custom 8-bit digital-to-analog pulse-width modulator that transforms PCM data into speaker-ready signals. It includes hardware-level saturation logic to prevent digital clipping distortion during high-volume transients.

Programmable Timer: Acts as the system's "Heartbeat," mapped to MMIO address 0x500, allowing software to dynamically adjust the sample rate.

The macOS Toolchain Mastery

Built a professional verification environment on macOS using Verilator to transpile RTL into high-speed C++ models. Managed complex environment headers (SDKROOT) and automated the build flow with a custom Makefile system to generate VCD (Value Change Dump) files for nanosecond-level waveform debugging in GTKWave.

Key Results

Zero

Sample Jitter

100%

ISA Compliance

1-Cycle

IRQ Latency

Future Work

  • DSP Accelerators: Adding hardware-accelerated FFT/FIR filter blocks.
  • Physical Hardening: Implementing the OpenLane flow for Sky130 Tape-out.
  • Multi-Channel Audio: Expanding to I2S protocols for 7.1 surround support.