Custom Audio SoC (RV32IM)

Project Overview

Designed and verified a custom RV32IM System-on-Chip (SoC), specifically optimized for real-time digital signal processing (DSP) and high-fidelity audio output. By implementing a hardware-accelerated multiplier and a deterministic single-cycle datapath, the system ensures cycle-perfect audio delivery without the sample jitter typical of complex OS-based processors.

The Challenge

Digital audio requires strict timing; any latency in sample delivery causes audible distortion. Standard software-based math (like volume scaling) can take dozens of cycles, risking "audio lag". My goal was to build a "Silicon-Up" solution where the hardware handles the heavy lifting—multiplying signals and triggering interrupts at precise nanosecond intervals.

Technical Approach

CPU Core & Interrupt Logic

Implemented a custom core in SystemVerilog following the RISC-V specification. Key features include:

• Hardware Vector Table: CPU performs a hardware-forced jump to 0x20 immediately upon timer IRQ.
• Context Management: Integrated MEPC registers to resume background tasks seamlessly after audio interrupts.
• Single-Cycle Determinism: Every instruction, including math, executes in exactly one clock cycle to ensure predictable timing.

Hardware-Accelerated Math (M-Extension)

Upgraded the ALU with a dedicated Hardware Multiplier unit. By shifting from software-based multiplication loops to dedicated hardware gates, I reduced multiplication latency from ~32 cycles down to 1 cycle. This enables real-time volume scaling and audio mixing with zero CPU overhead.

Audio Peripheral Design

Audio PWM Engine: A custom 8-bit digital-to-analog modulator that transforms PCM data into speaker-ready pulses, featuring hardware-level saturation logic to prevent clipping.

Precision Timer: Acts as the system's "Heartbeat," mapped to MMIO address 0x500, triggering interrupts exactly every 22 microseconds for 44.1kHz audio.

Verification & GTKWave Analysis

Built a professional verification environment on macOS using Verilator to simulate the RTL at GHz speeds. I used GTKWave to verify nanosecond-level timing, confirming that the multiplier calculates products instantly the moment a timer interrupt occurs.

Future Work

• DMA Controller: Offloading audio data transfers from the CPU to dedicated hardware for lower power consumption.
• Fixed-Point DSP: Updating the ALU to handle decimals for advanced reverb and EQ filters.

View Project on GitHub